Funkcje i opisy wyprowadzeń układów PLL

Oryginał pod adresem: https://www.rigpix.com/otherusefulinfo/pll_pins.htm

V_CC lub V_DD
Napięcie zasilania układu. Zwykle mieści się w granicach 4-8 V DC.

GND lub V_SS
Potencjał zera dla napięcia zasilania układu.

RI (Reference Oscillator input)
Podłączenie rezonatora kwarcowego zazyczaj o częstotliwości 10,240 MHz.

RO (Reference Oscillator output)
W większości układów kwarc jest po prostu połączony pomiędzy RI i RO, ponieważ chip ma wbudowany obwód oscylatora, który wymaga tylko kilku zewnętrznych kondensatorów. Jednak niektóre układy, takie jak PLL02A, nie mają wbudowanego oscylatora; w związku z tym nie ma pinu RO, a zewnętrznie wymagany jest aktywny oscylator tranzystorowy, który łączy się z RI.

1/2R
Wyjście dzielnika częstotliwości generatora odniesienia 10,240 MHz ÷ 2 = 5,12 MHz. Zwykle łączy się go z powielaczem częstotliwości, aby wytworzyć sygnał 15,360 MHz (5,12 MHz × 3), który można zmieszać z 16 MHz VCO, aby wytworzyć sygnał o niskiej częstotliwości do programowalnego dzielnika częstotliwości.

RB (Buffered output of the 10.240 MHz Reference Oscillator)
This signal, if present, can be used for mixing with the 10.695 MHz receiver first IF or mixing with the 16 MHz VCO during TX mode to provide the 455 kHz second IF (RX) or the direct on-channel TX frequency.

FIN
Input to the programmable divider which is coming from the output of the VCO. Sometimes called PI (Programmable Input) or DI (Divider Input) by some manufacturers. This is the actual downmix signal or direct VCO signal in the faster chips which will be compared to the Reference Divider's output in the Phase Detector. It is the change in this signal's frequency which forces the Phase Detector and VCO to correct until the loop locks.

DO (Phase Detector output)
Sometimes called "PO or PDOUT" (Phase Output) or "EO" (Error Output) by some manufacturers. This is the output which results from comparing RI and FIN. If the two inputs don't match exactly, this circuit sends a DC correction output to the Loop Filter/VCO until the loop corrects itself and locks up.

LD (Lock Detector)
Sometimes called "LM" (Lock Monitor) by some manufacturers.This is a second output of the phase detector which is used to kill the transmitter (and sometimes the receiver) if the loop is not locked and operating correctly. Some chips have more than one lock detector pin and thus you'll sometimes see LD1 and "LD2" on the specs. When two lock detectors are used, their normal outputs are usually opposite logic states; i.e., one LD ig normally 1 and the other is normally 0.This is a convenient design feature which allows the manufacturer some flexibility because he can have a choice of inhibiting circuits; some work with LOW outputs,some work with HIGH outputs. Some rigs use both LD pins in their circuits.

MC (Misprogram Code detector)
The same idea as the Lock Detector, this is found in the newer ROM chips. If you try to force an illegal program code on the chip, this pin is activated and will kill the transmitter, receiver, or in some cases, call up Ch.9 or Ch.19 instead.

T/R (Transmit/Receive switch)
This is used to provide the 455 kHz offset for the receiver's second IF stage in dual-conversion AM or FM rigs. Pressing the mike button changes this pin's logic state to its opposite state from the RX Mode.This shifts the ROM controlling the programmable divider, and in some chips also shifts the output of the reference divider from standard 5 kHz steps to 2.5 kHz steps. The T/R shift is the reason you`ll see two different sets of N-Codes and VCO frequencies in a rig's service manual. NOTE: Some manufacturers' chip spec sheets show a bar (-) above some pin functions, such as LM, T/R, etc. This bar is a digital logic symbol which indicates what state (1 or 0) that pin is in when activated. For example, the T/R with the bar notation means that the pin is normally HIGH ("1") in the receive mode and normally LOW ("0") in the transmit mode. /LM means the Lock Monitor is "active LOW". , i.e., it is normally HIGH but goes LOW if the loop is unlocked.

FS (Frequency Select)
This is a feature of some chips which allows them to synthesize frequencies in either 10 kHz CB steps, or 5 kHz steps. Remember, some older chips such as the PLLO2A were intended for other uses besides CB, such as VHF marine radios, aircraft radios, etc., where 5 kHz channel spacing is common. In addition, this feature often makes it easier to synthesize SSB frequencies as well as AM/FM although the feature hasn't been used much for this. Depending upon whether the chip has an internal pull-up or pull-down resistor here, it is generally connected to produce 10 kHz CB spacings in the older chips. The newer chips having a T/R shift must use the 5 kHz spacing when the T/R pin is also used. IMPORTANT: You can't use this function to get 5 kHz channel spacings, because the programmable divider must also change to match the spacing.

AI, AO (Active Loop Filter Amplifier input and output)
This circuit, if present, is used to smooth out the digital waveform coming from the phase detector, before it's applied to the VCO (See text.) This filter is found in the newer CB-only chips. The older chips (Eg, PLL02A) require external passive filters using capacitors and resistors. In many rigs you'll find that these pins are connected either directly or through a resistor so that they are placed in series between the phase detector output pin and the VCO input.

FIL (Active filter)
We're using this designation in certain very old chips when the exact spec sheets are not available but it's known from studying the chip's wiring in the rig that the pins are in fact part of a loop filter.

T oraz Q
This is a wave-shaping circuit found in a few NEC chips (uPD2810, uPD2814, uPD2816, and uPD2824). It adds design flexibility but is often not even connected. This circuit consists of an input amplifier and a flip-flop, and its purpose is to change a sine-wave input (T) to a square-wave output (Q) which is more compatible with digital electronic circuits.

P0 ... P10 (Program select pins from channel selector switch)
(Sometimes called "D" for Data rather than "P" for Program.) These pins control the actual channel selection. They may control selection through straight binary coding, BCD, or ROM. The sub-numbers indicate the weight or significance of each pin. For example if there were 8 programming pins, P1 to P8, P1 would be in the "least significant bit" and P8 would be the "most significant bit".The higher the sub-number, the greater the weight of that pin.

NC (No Connection)
An unused pin may actually be disconnected inside the chip, or simply not used for that particular rig' s PLL circuit.